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Design of Low Power Comparator Using DG Gate

Circuits and Systems
Vol. 5 No.1(2014), Article ID:41935,6 pages DOI:10.4236/cs.2014.51002

Design of Low Power Comparator Using DG Gate

Bahram Dehghan1*, Abdolreza Roozbeh2, Jafar Zare3

1Young Researchers and Elite Club, Sarvestan Branch, Islamic Azad University, Sarvestan, Iran

2Department of Electrical Engineering, Zarghan Branch, Islamic Azad University, Zarghan, Iran3Department of Electrical Engineering, Sarvestan Branch, Islamic Azad University, Sarvestan, Iran

Email: *[email protected] com

Copyright © 2014 Bahram Dehghan et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. In accordance of the Creative Commons Attribution License all Copyrights © 2014 are reserved for SCIRP and the owner of the intellectual property Bahram Dehghan et al. All Copyright © 2014 are guarded by law and by SCIRP as a guardian.

Received November 18, 2013; revised December 18, 2013; accepted December 25, 2013

Keywords: Reversible Logic Comparator; TR and DG Gate; Quantum Cost; Garbage Output

ABSTRACT

In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V+ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.

1. Introduction

Conventional combinational logic circuits dissipate heat for every bit of information that is lost during their operation [1]. According to Landauer’s principle, each bit of data lost produces kTln2 joules amount of heat, where k is Boltzmann’s constant and T is the absolute temperature at which the operation is implemented [2]. Moore’s law [3] previses exponential growth of the heat generated due to the information loss, which will be a significant amount of heat loss in the next decade.

Bennett [4] illustrated that zero energy dissipation would be possible only if the network based on reversible gates. Hence, reversibility will become a necessary property in future circuit design.

There are two Boolean constants, 0 and 1. Reversible circuits are those circuits that do not lose information.

These circuits can produce single output vector from each input vector, and conversely, there was a one-to-one mapping between output and input vectors. Hence, an N × N reversible gate can be represented as:

where Iv and Ov can be shown the input and output vectors respectively; the significant cost metrics in the synthesis of reversible logic circuits are the number of garbage outputs, delay and quantum cost [5,6]. Any unitary operation must be reversible. Thus, quantum networks effecting primary arithmetic operations such as addition, multiplication and exponentiation cannot be directly infered from their classical Boolean counterparts (classical logic gates such as AND or OR or EXOR are irreversible). Therefore, Quantum Arithmetic must be made from reversible logic combinations [7]. Various gates have been proposed over the last decades. Among them are the controlled-not (CNOT) introduced by Feynman [8] Toffoli [9], and Fredkin [10] gates. Digital Comparator is a combinational circuit that compares two inputs binary quantities (A and B) and produces outputs to indicate whether the inputs are equal or which input is greater than the other. Therefore, the circuit has three outputs to indicate whether A = B, A > B or A

In this paper, we present various designs of a three-bit comparator circuit using existing reversible logic gates. The present paper proposed a new gate, called reversible DG gate which was used in the design of comparator. All the comparators have been modeled and investigated using VHDL and Quartus II.

2. Basic Reversible Gates

The detailed cost of a reversible gate associates with any specific realization of quantum logic. A short description of the gates are given below.

A. The NOT Gate A NOT gate is a 1 × 1 gate performed as shown in Figure 1(a). It has quantum cost of 1.

B. The Controlled-V and Controlled-V+ Gates The Quantum cost of a Reversible gate is computed by counting the number of V, V+ and CNOT gates [11]. The controlled-V and V+ gates are shown in Figures 1(b) and (c).

The Controlled-V and Controlled-V+ quantum gates have some properties that are shown below:

(a)(b)(c)

Figure 1. a) Not gate; b) Controlled-V gate; c) ControlledV+ gate.

These equations depict that two V or V+ gates in series are equivalent to a NOT gate; and two V and V+ in series, are equivalent a BUFFER gate.

C. Feynman Gate The most popular (2, 2) one-through reversible gate is the Feynman gate [8]. The logical functions performed by a Feynman gate with input vector (A, B) and output vector (P, Q) are represented in Figure 2.

The input double (A, B) depends on its output double (P, Q) as follows.

If A = 0 then Q would be equal to B. If A = 1 then showed the complement of the input (B).

Hence, it is called as quantum XOR and also called as CNOT (1-NOT).

D. Fredkin gate Fredkin gate [10], depicted in Figure 3, is a (3, 3) reversible gate which penetrates P = A, Q = A’B ⊕ AC and R = A’C ⊕ AB where (A, B, C) is the input vector and (P, Q, R) is the output vector.

Figures 4(a) and (b) offer the performance of the Fredkin gate as AND and OR functions respectively.

E. New gate The New gate [12] is a (3, 3) reversible gate. The most significant aspect of this gate is that it can work as a universal gate.

Figure 2. Feynman gate.

Figure 3. Fredkin gate.

(a)(b)

Figure 4. Fredkin gate as a) AND function; b) OR function.

The New gate is one of the most popular reversible as represented in Figure 5.

F. BVF gate This is a (4, 4) reversible logic gate [13] shown in Figure 6 with input vector I (A, B, C, D) and the output vector is O (P, Q, R, S) . This can be used for duplication of the required inputs to meet the fan-out requirements. This gate can be specified by P = A, Q = A ⊕ B, R = C and S = C ⊕ D.

G. TR gate Recently Thapliyal and Ranganathan in [14]  have proposed  a new design of the reversible full subtractor based on the offered quantum gates implementation of the TR gate. TR gate with quantum cost of 4. The quantum cost of TR gate is 4 since it requires 1 V+ gates, 2 V gate and 1 CNOT gate in its structure.

TR gate and Quantum implementation of TR gate have represented in Figures 7(a) and (b) respectively.

3. Proposed Gate

This paper presents a new (3, 3) reversible gate, “DG”,

Figure 5. New gate.

Figure 6. BVF gate [13].

(a)(b)

Figure 7. a) TR gate as a reversible half subtractor; b) Quantum implementation of TR gate based reversible half subtractor.

with inputs (A, B, C) and outputs P = A, Q = (A ⊕ B)’, R = AB’ ⊕ C that is shown in Figure 8(a). The gate is one-through, which means one of the input variables is also output. The corresponding truth table of DG gate is shown in Table 1. Figure 8(b) shows the quantum implementation of the DG with quantum cost of 5. The corresponding truth table of the DG gate is shown in Table 1.

4. Design of the Three Bit Comparator

The two numbers are equal if all pairs of significant digits are equal; meaning A3 = B3 and A2 = B2 and A1 = B1.

To check for this equality, we use the XNOR gate as we did previously.

So we have seen three bit comparator (A = B) using classical gates as shown in Figure 9.

In the same way, the following classical gate A > B can be considered for a three bit comparator which is shown in Figure 10.

(a)(b)

Figure 8. a) DG gate; b) Quantum implementation of DG gate.

Table 1. Truth table for the DG gate.

Figure 9. Three bit comparator (A = B) using classical gates.

Figure 10. Three bit comparator (A > B) using classical gates.

If we want to have the output A = B, DG and BVF Gates can be used. The results are shown in Figure 11. Table 2 shows the evaluation of the mentioned circuit.

Two DG Gates can be put instead of BVF Gate to reduce the number of gates. The results are shown in Figure 12. Table 3 shows the evaluation of the mentioned circuit.

Reversible three bit comparator is implemented with various types of reversible logic gates as shown in Figures 13 and 14 respectively.

The proposed circuit of the three bit comparator is evaluated in terms of number of reversible gates used and garbage outputs generated. Tables 4 and 5 show the evaluation of the proposed circuits.

The results show that DG gate reduces the number of gates and garbage outputs.

In the proposed one-bit comparator design, we have investigated FA > B and FA = B and the third condition FA

The results are shown in Figure 15. DG gate is used in Figure 15 where DG and NG are used in Figure 10.

Figure 16 has less garbage outputs but in Figure 15, there are EXOR and EXNOR gates in outputs concur-

Figure 11. One bit (A = B) using BVF, DG Gates.

Figure 12. One bit (A = B) using DG gate.

Figure 13. Three bit comparator using TR gate.

Figure 14. Three bit comparator using DG gate.

Table 2. Evaluation of the proposed comparator.

Figure 15. One bit comparator using DG gate.

Figure 16. One bit comparator using DG gate and NEW gate.

Table 3. Evaluation of the proposed comparator.

Table 4. Evaluation of the proposed comparator.

Table 5. Evaluation of the proposed comparator.

rently. Tables 6 and 7 show the evaluation of the proposed circuits.

In the mentioned paper one bit comparator has better function in comparison with Nagamani et al. Figure 17 is selected as follows, in Nagamani et al.

A good synthesis for reversible logic should not create an excessive “garbage” or “waste of outputs”. Hence, the components are chosen so that the designed scheme has the desired characteristics. One bit comparator can be represented by 2 DG gates and 1 FG gate, as shown in Figure 18. This structure can be utilized for testing outputs 1 and 3 (AB’). DG gate operates as a signal copying that shown in Figure 18. The corresponding table of mentioned circuit is shown in Table 8. The (A’B) output of the Figure 18 is given by the equation:

Figure 18 has better performance because of similarity gates and two same outputs. Although garbage outputs seems zero. Table 8 shows the evaluation of the mentioned circuit.

Two same outputs of this Figure can be used for concurrent error detection.

Figure 17. One bit comparator using R gate and BJN gate [1].

Figure 18. One bit comparator using DG gate.

Table 6. Evaluation of the proposed comparator.

Table 7. Evaluation of the proposed comparator.

Table 8. Evaluation of the proposed comparator.

5. Simulation Results

Reversible logic gates are extensively known to be compatible with future computing technologies which approximately dissipate zero heat [15]. For example, Reversible three bit comparators offered using VHDL and Simulated using Quartus II Simulator. Simulation results are shown in Figures 19(a) and (b). For one bit comparator using DG gate result shown in Figure 19(c).

6. Discussions and Conclusions

Conventional computers generate heat and waste much energy. In order to make a computer faster and lower power, consumption proposed reversible logic gates. In this paper, we have presented new designs of reversible one and three-bit comparators based on the quantum gates implementation of the reversible TR and DG. The main goal of this paper is optimized in terms of number of garbage outputs, gate count and quantum cost for comparator designs. The proposed DG gate can be combined with TR gate and various types of reversible logic gates to design minimal quantum cost and garbage less reversible circuits.

The newly proposed DG gate can be used for imple-

(a) (b) (c)

Figure 19. a) Three bit comparator a > b; b) Three bit comparator a = b; c) one bit comparator using DG gate.

menting concurrent EXOR and EXNOR output functions. Hence, three outputs of DG gate have efficient results for comparator designs. In this paper, one-bit comparator has better performance comparatively.

REFERENCES

  1. A. N. Nagamani, H. V. Jayashree and H. R. Bhagyalakshmi, “Novel Low Power Comparator Design Using Reversible Logic Gates,” 2011 Indian Journal of Computer Science and Engineering (IJCSE), Vol. 2, No. 4, 2011, pp. 566-574.
  2. R. Landauer, “Irreversibility and Heat Generation in the Computational Process,” IBM Journal of Research and Development, Vol. 5, No. 3, 1961, pp. 183-191. http://dx.doi.org/10.1147/rd.53.0183
  3. G. E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics, Vol. 38, No. 8, 1965.
  4. C. H. Bennett, “Logical Reversibility of Computation,” IBM Journal of Research and Development, Vol. 17, 1973, pp. 525-532.
  5. M. Mohammadi and M. Eshghi, “On Figureures of Merit in Reversible and Quantum Logic Designs,” Quantum Information Processing, Vol. 8, No. 4, 2009, pp. 297-318. http://dx.doi.org/10.1007/s11128-009-0106-0
  6. D. Maslov and G. W. Dueck, “Improved Quantum Cost for n-Bit Toffoli Gates,” IEEE Electronics Letters, Vol. 39, No. 25, 2003, pp. 1790-1791. http://dx.doi.org/10.1049/el:20031202
  7. V. Vedral, A. Bareno and A. Ekert, “Quantum Networks for Elementary Arithmetic Operations,” 1995. arXiv:quantph/9511018 v1
  8. R. Feynman, “Quantum Mechanical Computers,” Optic News, Vol. 11, 1985, pp. 11-20. http://dx.doi.org/10.1364/ON.11.2.000011
  9. T. Toffoli, “Reversible Computing,” Tech memo MIT/ LCS/TM-151, MIT Lab for Comp. Sci, 1980.
  10. E. Fredkin and T. Toffoli, “Conservative Logic,” International Journal of Theoretical Physics, Vol. 21, No. 3-4, 1982, pp. 219-253. http://dx.doi.org/10.1007/BF01857727
  11. H. G. Rangaraju, V. Hegde, K. B. Raja and K. N. Muralidhara, “Design of Efficient Reversible Binary Comparator,” International Conference on Communication Technology and System Design, 7-9 December 2011.
  12. M. H. Azad Khan Md., “Design of Full Adder with Reversible Gate,” International Conference on Computer and Information Technology, Dhaka, 27-28 December 2002, pp. 515-519.
  13. H. R. Bhagyalakshmi and M. K. Venkatesha, “Design of a Multifunction BVMF Reversible Logic Gate and Its Applications,” International Journal of Computer Applications (0975-8887), Vol. 32, No. 3, 2011.
  14. H. Thapliyal and N. Ranganathan, “A New Design of the Reversible Subtractor Circuit,” 2011 11th IEEE International Conference on Nanotechnology, Portland Marriott, 15-18 August 2011.
  15. B. Dehghan, “Survey the Inverse Property of Quantum Gates for Concurrent Error Detection,” Journal of Basic and Applied Scientific Research, 2013, pp. 603-608.

NOTES

*Corresponding author.

(PDF) Design of Low Power Comparator Using DG Gate

B. DEHGHAN ET AL.

OPEN ACCESS CS

(a)

(b)

(c)

Figure 19. (a) Three bit comparator a > b; (b) Three bit

comparator a = b; (c) one bit comparator using DG gate.

menting concurrent EXOR and EXNOR output functions.

Hence, three outputs of DG gate have efficient results for

comparator designs. In this paper, one-bit comparator has

better performance comparatively.

REFERENCES

[1] A. N. Nagamani, H. V. Jayashree and H. R. Bhagyalak-

shmi, “Novel Low Power Comparator Design Using Re-

versible Logic Gates,” 2011 Indian Journal of Computer

Science and Engineering (IJCSE), Vol. 2, No. 4, 2011, pp.

566-574.

[2] R. Landauer, “Irreversibility and Heat Generation in the

Computational Process,” IBM Journal of Research and

Development, Vol. 5, No. 3, 1961, pp. 183-191.

http://dx.doi.org/10.1147/rd.53.0183

[3] G. E. Moore, “Cramming More Components onto Inte-

grated Circuits,” Electronics, Vol. 38, No. 8, 1965.

[4] C. H. Bennett, “Logical Reversibility of Computation,”

IBM Journal of Research and Development, Vol. 17, 1973,

pp. 525-532.

[5] M. Mohammadi and M. Eshghi, “On Figureures of Merit

in Reversible and Quantum Logic Designs,” Quantum In-

formation Processing, Vol. 8, No. 4, 2009, pp. 297-318.

http://dx.doi.org/10.1007/s11128-009-0106-0

[6] D. Maslov and G. W. Dueck, “Improved Quantum Cost

for n-Bit Toffoli Gates,” IEEE Electronics Letters, Vol.

39, No. 25, 2003, pp. 1790-1791.

http://dx.doi.org/10.1049/el:20031202

[7] V. Vedral, A. Bareno and A. Ekert, “Quantum Networks

for Elementary Arithmetic Operations,” 1995.

arXiv:quantph/9511018 v1

[8] R. Feynman, “Quantum Mechanical Computers,” Optic

News, Vol. 11, 1985, pp. 11-20.

http://dx.doi.org/10.1364/ON.11.2.000011

[9] T. Toffoli, “Reversible Computing,” Tech memo MIT/

LCS/TM-151, MIT Lab for Comp. Sci, 1980.

[10] E. Fredkin and T. Toffoli, “Conservative Logic,” Interna-

tional Journal of Theoretical Physics, Vol. 21, No. 3-4,

1982, pp. 219-253.

http://dx.doi.org/10.1007/BF01857727

[11] H. G. Rangaraju, V. Hegde, K. B. Raja and K. N. Mura-

lidhara, “Design of Efficient Reversible Binary Compa-

rator,” International Conference on Communication Tech-

nology and System Design, 7-9 December 2011.

[12] M. H. Azad Khan Md., “Design of Full Adder with Re-

versible Gate,” International Conference on Computer and

Information Technology, Dhaka, 27-28 December 2002,

pp. 515-519.

[13] H. R. Bhagyalakshmi and M. K. Venkatesha, “Design of

a Multifunction BVMF Reversible Logic Gate and Its

Applications,” International Journal of Computer Appli-

cations (0975-8887), Vol. 32, No. 3, 2011.

[14] H. Thapliyal and N. Ranganathan, “A New Design of the

Reversible Subtractor Circuit,” 2011 11th IEEE Interna-

tional Conference on Nanotechnology, Portland Marriott,

15-18 August 2011.

[15] B. Dehghan, “Survey the Inverse Property of Quantum

Gates for Concurrent Error Detection,” Journal of Basic

and Applied Scientific Research, 2013, pp. 603-608.

Analytic Solution for Symmetric DG MOSFETs with Gate-Oxide-Thickn…: Ingenta Connect

An analytic solution for undoped (or lightly doped) symmetric DG (SDG) MOSFETs with small gate-oxide-thickness asymmetry is presented using Poisson’s equation considering only the mobile charge term and Taylor series expansion. The existing analytic models for symmetric DG MOSFETs have
been derived assuming the two gates are perfectly symmetric. In reality, the thicknesses of the two gate oxides are most likely slightly different due to process variations and uncertainties which can affect surface potential and other parameters of SDG MOSFETs. Therefore, it is very much
essential to provide a model for estimating the severity of this gate-oxide-thickness deviation in the performance of SDG MOSFETs. The effects on the gate capacitance of SDG MOSFET performance caused by small asymmetric oxide thickness due to process variations and uncertainties is studied.
The model can more accurately detect the errors on the performance of the SDG MOSFET with small gate-oxide-thickness asymmetry than as reported by Chang et al.

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Keywords:
DOUBLE-GATE (DG) MOSFET;
GATE-OXIDE-THICKNESS ASYMMETRY;
SURFACE POTENTIAL

Document Type: Research Article

Publication date:
October 1, 2011

More about this publication?

  • Journal of Computational and Theoretical Nanoscience is an international peer-reviewed journal with a wide-ranging coverage, consolidates research activities in all aspects of computational and theoretical nanoscience into a single reference source. This journal offers scientists and engineers peer-reviewed research papers in all aspects of computational and theoretical nanoscience and nanotechnology in chemistry, physics, materials science, engineering and biology to publish original full papers and timely state-of-the-art reviews and short communications encompassing the fundamental and applied research.

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The Malazan Fallen – Group Read – Deadhouse Gates: DG – Chapter Twenty Three

Mod

And Kalam gets a face to face – or rather face to corpse encounter with the Empress. And from this encounter we learn a few other things – though we have to decide how much we are to believe Laseen.

Firstly the battle of Pale. Laseen says that the decimation of the Bridgeburners was not part of the plan. That it was rather Tayschrenn’s failure of judgement.

Laseen’s tone hardened. ‘High Mage Tayschrenn’s efforts in Genabackis were misguided. The decimation of the Bridgeburners was not a part of my intentions. Within your squad was a young woman, possessed by a god that sought to kill me. Adjunct Lorn was sent to deal with her—’

In other words, Laseen asserts that Tayschrenn got carried away and overstepped himself diverting from the plan in going after Sorry, by taking the “scattergun” approach.

We get direct confirmation that Dujek’s outlawing was a ruse thought up by Onearm himself which she agreed to

We perceived the threat that was the Pannion Domin. Dujek, however, was of the opinion that he could not deal with it on his own. We needed to fashion allies of enemies, Kalam. We needed Darujhistan’s resources, we needed Caladan Brood and his Rhivi and Barghast, we needed Anomander Rake and his Tiste Andii. And we needed the Crimson Guard off our backs…

…But the question of trust remained problematic. I agreed to Dujek’s plan to cut him and his Host loose. As outlaws, they are, in effect, distanced from the Malazan Empire and its desires – our answer, if you will, to the issue of trust.’

We learn that Tayschrenn is now working under Dujek

Tayschrenn is Dujek’s – how do you soldiers say it – his shaved knuckle in the hole.’

But Kalam has other beefs. The killing of the Emperor, Dancer, Dassem Ultor and others. All of which she answers were for the good of the Empire.

Ultimately, it is none of these arguments that convince Kalam to end his quest to assassinate her.
He decides based on her obvious anger and passion when it comes to what is being done to the Malazan Army and citizens in Seven Cities.

‘Seven Cities—’
‘Will be answered in kind,’ she snapped.
Despite himself, the assassin’s eyes widened at the anger he heard there. Well, what do you know! Empress, you did not need your illusions after all. Thus, the hunt ends here. He sheathed the knife.

Kalam explains

‘You could have begged for your life. You could have given more reasons, made more justifications. Instead, you spoke, not with your voice, but with an empire’s.’

It was her genuine anger at the events in Seven Cities that convinces Kalam that Laseen acts for the empire and not merely(or not only) for her own selfish ends.

Laseen allows Kalam to leave and even tries to get the Claw to back off their own vendetta – which lends some credibility to her motives.

GaN-based double-gate (DG) sub-10-nm MOSFETs: effects of gate work function

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  • dg gate For convenience and safety Smart Devices

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    The Brandenburg Gate is … What is the Brandenburg Gate?

    Request “Brandenburg Gate” is redirected here; cm.also other meanings.

    Coordinates: 52 ° 30’58.68 ″ s. NS. 13 ° 22′39.72 ″ in. d. / 52.5163 ° N NS. 13.3777 ° E d. (G) (O) 52.5163, 13.3777

    Brandenburg Gate, view from the east side

    View of the gate from the Reichstag, March 5, 1990 (part of the Berlin Wall is visible in the center and behind the gate)

    Brandenburg Gate

    Brandenburg Gate in Berlin

    Brandenburg Gate (German Brandenburger Tor ) is an architectural monument in the center of Berlin in the Mitte district.It was created in 1788-1791.

    History

    The Brandenburg Gate, which celebrated its 220th anniversary, is the most famous symbol of Berlin and Germany. For many years they served as a symbol of the divided Germany and Berlin, and after 1989 they became the embodiment of the reunification of the country.

    The Brandenburg Gate is the only surviving city gate in Berlin, its original name was Peace Gate . They were built by Karl Gottgard Langgans in 1789-1791.and is the first significant work performed in the style of Berlin classicism. The example for the Brandenburg Gate was the Propylaea of ​​the Acropolis in Athens. The facade of the gate was originally painted white. The decoration of the facade belongs to the hand of Johann Gottfried Schadov; he also designed a six-meter quadriga, which is ruled by the goddess of Victory Victoria (the quadriga is deployed to the east).

    After conquering Berlin, Napoleon ordered the chariot to be dismantled and transported to Paris. After the victory over Napoleon, the goddess Victoria returned to Berlin and received the Iron Cross, created by Friedrich Schinkel.

    In 1871, victorious soldiers marched through the gate, in 1918 and 1920. – counter-revolutionary soldiers, in 1933 the gate became the backstage of the National Socialist holiday.

    During the Second World War, the Brandenburg Gate was seriously damaged, the quadriga was completely destroyed. From 1945 to 1957, the flag of the USSR fluttered on the quadriga, which was then replaced by the flag of the GDR (since 1989, after the unification of Germany, there is no flag on the gate).

    In 1956, the gate was restored, the quadriga was restored only by 1958.On August 13, 1961, a wall blocked the passage through the gate. The gates were located on the territory of East Berlin (the wall in this place seemed to “protrude” into the territory of West Berlin), and citizens from West Berlin could not get to the gates themselves. But ordinary residents of East Berlin also did not have access to the gates, since they were fenced off from the eastern part by a “mini-wall”. On New Year’s Eve 1989, the quadriga suffered from excessive expressions of joy at the unification of the country. In August 1991, the restored sculptural group returned to its rightful place.

    When East and West Berlin were separated by the Berlin Wall, the Brandenburg Gate was isolated from other buildings, but today it fits perfectly into the architecture of the restored buildings of Paris Square. On the north side of the square are the Dresdner Bank and the French Embassy, ​​on the south side – DG-Bank, the Academy of Arts and the luxury hotel Adlon.

    References

    residential complex Moskovskie Vorota: variatika – LiveJournal

    Design of an apartment in the residential complex Moskovskie Vorota.Area 88 sq.m. Apartment of 99 m² with three bedrooms and a kitchen-living room. Customers are a family with three sons. It was originally planned to decorate the renovation from the developer. But due to the low quality of repairs, in the end, they decided on more global changes.

    Furniture: Geos Ideal, Ikea, DG home, Sonberry, Tashoti, Kreslo, Geniuspark, Zara home, Ogogo, Amikovry.

    Light: Lightstar, Ideallux, Shuller, Artelamp, Osgona, Newport, Crystal Lux, Mantra.

    Wall decoration: Dulux, Atlantis, Sirpi, BN International, Midbec, Scion.

    Doors: Volkhovets.

    Tile: Greta Wolfe.

    The overhang of the load-bearing wall behind the sofa is beaten by a small bookcase with open shelves. Its back wall is mirrored, which creates an interesting effect, as if there is still space behind it. The pastel lilac velvet of the sofa is highlighted with lilac accents in the decor.

    In the kitchen-living room, the corner kitchen turns into a TV cabinet.The kitchen apron is made of an unusual hexagonal tile by Greta Wolfe. The dining group is located at the entrance to the room next to the ledge of the vent channel. For the walls, we chose companion wallpaper in gray-blue and cream colors. All rooms have a ceiling cornice with hidden lighting.

    At the entrance to the bedroom, a walk-through dressing room with closed wardrobes was made. Some wardrobes have glass doors behind which clothes are visible.A large illuminated mirror is installed above the chest of drawers in the dressing room. The result is a dressing table with a small ottoman.

    The wall behind the headboard is decorated with geometric wallpaper. Along the edges are mirrored bedside tables, which dissolve against the background of mirrored panels. Hanging chrome lamps save space on bedside tables. The bedroom is combined with a loggia, which has enough space for a large work desk.The walls of the loggia are decorated with brick-like tiles.

    The nursery for the eldest son is made in neutral colors with the addition of deep blue and brick colors. A large desk with storage system is custom made. For decoration, illustrations of custom Soviet cars by artist Andrei Tkachenko were used.

    The nursery for the younger and middle son turned out to be brighter.Beds with headboards are separated from each other by a low shelving unit. Light roman blinds combined with thick curtains were chosen for window decoration. Roman shades will not get in the way during the day. A special mount is used for wall decor, you can move and replace posters without damaging the walls.

    A large mirrored wardrobe was made in the corridor. The outer corners of the walls are covered with polyurethane moldings to protect the corner.

    90,000 OSCE SMM observers from the forward patrol base in Horlivka resumed monitoring in ORDO

    The OSCE Special Monitoring Mission resumed patrolling from its forward patrol base in Horlivka after being blocked by the DPR occupants at a local hotel. This is stated in the report of the OSCE SMM on October 19.

    “At 15:40 on 18 October, the Mission noted that the previously fixed padlock and chain had been removed from the vehicle gates of the Mission’s Forward Patrol Base (FSP) in Horlivka and that these gates had been opened.In front of the PPB building, the observers saw a previously erected tent, but did not record people and vehicles nearby. The SMM left the Mission BCP to conduct patrols and returned at 16:03, ”the observers reported.

    The Mission recalled that the decision of the OSCE Permanent Council No. 1117 provides for the provision of safe and reliable access for the Mission throughout Ukraine. Unrestricted and unconditional access to all areas is critical to ensure effective monitoring and reporting of the security situation, as well as other mandated tasks.In addition, the Mission is mandated to report any restrictions on the SMM’s freedom of movement or other circumstances impeding the fulfillment of its mandate.

    Let us remind you that on October 13 the fighters of the Armed Forces of Ukraine detained a militant “LPR”, who, covering his activities with the identification marks of the JCCC, was conducting reconnaissance in the area of ​​the Ukrainian positions. The occupation authorities of the ORDLO accused the OSCE SMM of inaction, demanded the release of the militant and organized blocking of the hotel where the Mission staff lived.In turn, the European observers explained that they had not seen the moment of the arrest. The SMM knows that the “LPR” representative in the JCCC was allegedly “taken hostage” only from the words of the leadership of the illegal armed groups.

    In addition, the OSCE SMM never said that they recognize some representatives of the “DPR / LPR” in the JCCC. The puppet authorities of the “republics” appropriated this status after the departure of Russian officers in December 2017. The occupiers announced the creation of their own “representations” at the Joint Center for Control and Coordination of the Ceasefire Regime and expressed a desire to cooperate with the OSCE mission.Officially, there are no representations of terrorist “republics” in the Joint Center and cannot be. They are formally referred to by the Mission as “members of the armed formations with armbands bearing the words“ JCCC ”.

    On Saturday, about 200 pro-Russian protesters went to a meeting with OSCE observers, demanding the release of an officer of the illegal armed formations of the “LPR”, detained by the Ukrainian military last week. The mission has already faced protests organized by Moscow-backed separatists, but this time, demonstrators blocked the entrance to the hotel where the observers are based.

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